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1 BSZ0910ND rev.2.0,2017-11-23 final data sheet powerstage3x3 mosfet powerstage3x3 features dualn-channeloptimos?mosfet enhancementmode logiclevel(4.5vrated) avalancherated 100%lead-free;rohscompliant halogen-freeaccordingtoiec61249-2-21 table1keyperformanceparameters parameter value unit v ds 30 v r ds(on),max 9.5 m w i d 25 a q oss 4.6 nc q g (0v..4.5v) 4.0 nc type/orderingcode package marking relatedlinks BSZ0910ND pg-wison-8 0910nd - vphase
2 powerstage3x3 BSZ0910ND rev.2.0,2017-11-23 final data sheet tableofcontents description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 electrical characteristics diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 vphase
3 powerstage3x3 BSZ0910ND rev.2.0,2017-11-23 final data sheet 1maximumratings at t a =25c,unlessotherwisespecified,onetransistoractive table2maximumratings values min. typ. max. parameter symbol unit note/testcondition continuous drain current i d - - - - - - - - 25 11.1 9.5 5.7 a v gs =10v, t c =25c v gs =10v, t a =25c 1) v gs =4.5v, t a =25c 1) v gs =4.5v, t a =25c 2) pulsed drain current 3) i d,pulse - - 40 a t a =25c avalanche energy, single pulse 4) e as - - 20 mj i d =9a, r gs =25 w gate source voltage v gs -20 - 20 v - power dissipation p tot - - - - 31 1.9 w t c =25c t a =25c, r thja =65c/w 1) operating and storage temperature t j , t stg -55 - 150 c iec climatic category; din iec 68-1: 55/150/56 2thermalcharacteristics table3thermalcharacteristics values min. typ. max. parameter symbol unit note/testcondition thermal resistance, junction - case, bottom r thjc - - 4 c/w - device on pcb, 6 cm2 cooling area 1) r thja - - 65 c/w - device on pcb, minimal footprint 2) r thja - - 180 c/w - 1) device on 40 mm x 40 mm x 1.5 mm epoxy pcb fr4 with 6 cm 2 (one layer, 70 m thick) copper area for drain connection. pcb is vertical in still air. 2) device mounted on a minimum pad (one layer, 70 m thick) 3) see diagram 3 for more detailed information 4) see diagram 13 for more detailed information vphase
4 powerstage3x3 BSZ0910ND rev.2.0,2017-11-23 final data sheet 3electricalcharacteristics table4staticcharacteristics values min. typ. max. parameter symbol unit note/testcondition drain-source breakdown voltage v (br)dss 30 - - v v gs =0v, i d =1ma gate threshold voltage v gs(th) 1.2 1.6 2 v v ds = v gs , i d =250a zero gate voltage drain current i dss - - - 10 1 - a v ds =30v, v gs =0v, t j =25c v ds =30v, v gs =0v, t j =125c gate-source leakage current i gss - - 100 na v gs =20v, v ds =0v drain-source on-state resistance r ds(on) - - 7.7 10.3 9.5 13.0 m w v gs =10v, i d =9a v gs =4.5v, i d =9a gate resistance 1) r g 1.8 3.5 7 w - transconductance g fs - 33 - s | v ds | 3 2| i d | r ds(on)max , i d =9a table5dynamiccharacteristics values min. typ. max. parameter symbol unit note/testcondition input capacitance 1) c iss - 590 800 pf v gs =0v, v ds =15v, f =1mhz output capacitance 1) c oss - 170 230 pf v gs =0v, v ds =15v, f =1mhz reverse transfer capacitance 1) c rss - 21 - pf v gs =0v, v ds =15v, f =1mhz turn-on delay time t d(on) - 6.2 - ns v dd =15v, v gs =10v, i d =9a, r g,ext =6 w rise time t r - 3.2 - ns v dd =15v, v gs =10v, i d =9a, r g,ext =6 w turn-off delay time t d(off) - 18.5 - ns v dd =15v, v gs =10v, i d =9a, r g,ext =6 w fall time t f - 2.8 - ns v dd =15v, v gs =10v, i d =9a, r g,ext =6 w table6gatechargecharacteristics 2) values min. typ. max. parameter symbol unit note/testcondition gate to source charge q gs - 1.5 - nc v dd =15v, i d =9a, v gs =0to4.5v gate charge at threshold q g(th) - 0.9 - nc v dd =15v, i d =9a, v gs =0to4.5v gate to drain charge q gd - 1.0 - nc v dd =15v, i d =9a, v gs =0to4.5v switching charge q sw - 1.5 - nc v dd =15v, i d =9a, v gs =0to4.5v gate charge total 1) q g - 4.0 5.6 nc v dd =15v, i d =9a, v gs =0to4.5v gate plateau voltage v plateau - 2.6 - v v dd =15v, i d =9a, v gs =0to4.5v gate charge total 1) q g - 8.2 11.4 nc v dd =15v, i d =9a, v gs =0to10v gate charge total, sync. fet q g(sync) - 3.4 - nc v ds =0.1v, v gs =0to4.5v output charge 1) q oss - 4.6 - nc v dd =15v, v gs =0v 1) defined by design. not subject to production test. 2) see 2 gate charge waveforms 2 for parameter definition vphase
5 powerstage3x3 BSZ0910ND rev.2.0,2017-11-23 final data sheet table7reversediode values min. typ. max. parameter symbol unit note/testcondition diode continuous forward current i s - - 25 a t c =25c diode pulse current i s,pulse - - 40 a t c =25c diode forward voltage v sd - 0.86 1.1 v v gs =0v, i f =9a, t j =25c reverse recovery charge 1) q rr - 5 - nc v r =15v, i f =9a,d i f /d t =100a/s 1) defined by design. not subject to production test. vphase
6 powerstage3x3 BSZ0910ND rev.2.0,2017-11-23 final data sheet 4electricalcharacteristicsdiagrams diagram1:powerdissipation t a [c] p tot [w] 0 20 40 60 80 100 120 140 160 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 p tot =f( t a ),minimalfootprint diagram2:draincurrent t a [c] i d [a] 0 20 40 60 80 100 120 140 160 0 1 2 3 4 5 6 7 8 10v 4.5v i d =f( t a );minimalfootprint diagram3:safeoperatingarea v ds [v] i d [a] 10 -1 10 0 10 1 10 2 10 -2 10 -1 10 0 10 1 10 2 1 s 10 s 100 s 1 ms 10 ms dc i d =f( v ds ); t c =25c; d =0;parameter: t p diagram4:max.transientthermalimpedance t p [s] z thjc [k/w] 10 -6 10 -5 10 -4 10 -3 10 -2 10 -1 10 -1 10 0 10 1 single pulse 0.01 0.02 0.05 0.1 0.2 0.5 z thjc =f( t p );parameter: d = t p / t vphase
7 powerstage3x3 BSZ0910ND rev.2.0,2017-11-23 final data sheet diagram5:typ.outputcharacteristics v ds [v] i d [a] 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 5 10 15 20 25 30 35 40 3.5 v 4 v 4.5 v 5 v 10 v 3 v 2.8 v i d =f( v ds ), t j =25c;parameter: v gs diagram6:typ.drain-sourceonresistance i d [a] r ds(on) [m w ] 0 5 10 15 20 25 30 35 40 0 4 8 12 16 20 24 2.8 v 3 v 3.5 v 4 v 4.5 v 5 v 10 v r ds(on) =f( i d ), t j =25c;parameter: v gs diagram7:typ.transfercharacteristics v gs [v] i d [a] 0 1 2 3 4 5 0 5 10 15 20 25 30 35 40 150 c 25 c i d =f( v gs ),| v ds |>2| i d | r ds(on)max ;parameter: t j diagram8:typ.drain-sourceonresistance v gs [v] r ds(on) [m w ] 0 2 4 6 8 10 0 4 8 12 16 20 24 150 c 25 c r ds(on) =f( v gs ), i d =9a;parameter: t j vphase
8 powerstage3x3 BSZ0910ND rev.2.0,2017-11-23 final data sheet diagram9:normalizeddrain-sourceonresistance t j [c] r ds(on) (normalizedto25c) -80 -40 0 40 80 120 160 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 r ds(on) =f( t j ), i d =9a, v gs =10v diagram10:typ.gatethresholdvoltage t j [c] v gs(th) [v] -80 -40 0 40 80 120 160 0.0 0.4 0.8 1.2 1.6 2.0 2500 a 250 a v gs(th =f( t j ), v gs = v ds ;parameter: i d diagram11:typ.capacitances v ds [v] c [pf] 0 5 10 15 20 25 30 10 1 10 2 10 3 ciss coss crss c =f( v ds ); v gs =0v; f =1mhz diagram12:forwardcharacteristicsofreversediode v sd [v] i f [a] 0.00 0.25 0.50 0.75 1.00 1.25 1.50 10 -1 10 0 10 1 10 2 25 c 25 c, max 150 c 150 c, max i f =f( v sd );parameter: t j vphase
9 powerstage3x3 BSZ0910ND rev.2.0,2017-11-23 final data sheet diagram13:avalanchecharacteristics t av [s] i av [a] 10 0 10 1 10 2 10 3 10 -1 10 0 10 1 10 2 25 c 100 c 125 c i as =f( t av ); r gs =25 w ;parameter: t j,start diagram14:typ.gatecharge q gate [nc] v gs [v] 0 2 4 6 8 10 0 2 4 6 8 10 6 v 15 v 24 v v gs =f( q gate ), i d =9apulsed, t j =25c;parameter: v dd diagram15:drain-sourcebreakdownvoltage t j [c] v br(dss) [v] -80 -40 0 40 80 120 160 28 29 30 31 32 33 34 v br(dss) =f( t j ); i d =1ma vphase gate charge waveforms
10 powerstage3x3 BSZ0910ND rev.2.0,2017-11-23 final data sheet 5packageoutlines figure1outlinepg-wison-8,dimensionsinmm/inches vphase gate charge waveforms
11 powerstage3x3 BSZ0910ND rev.2.0,2017-11-23 final data sheet revisionhistory BSZ0910ND revision:2017-11-23,rev.2.0 previous revision revision date subjects (major changes since last revision) 2.0 2017-11-23 release of final version trademarksofinfineontechnologiesag aurix?,c166?,canpak?,cipos?,coolgan?,coolmos?,coolset?,coolsic?,corecontrol?,crossave?,dave?,di-pol?,drblade?, easypim?,econobridge?,econodual?,econopack?,econopim?,eicedriver?,eupec?,fcos?,hitfet?,hybridpack?,infineon?, isoface?,isopack?,i-wafer?,mipaq?,modstack?,my-d?,novalithic?,omnitune?,optiga?,optimos?,origa?,powercode?, primarion?,primepack?,primestack?,profet?,pro-sil?,rasic?,real3?,reversave?,satric?,sieget?,sipmos?,smartlewis?, solidflash?,spoc?,tempfet?,thinq?,trenchstop?,tricore?. trademarksupdatedaugust2015 othertrademarks allreferencedproductorservicenamesandtrademarksarethepropertyoftheirrespectiveowners. welistentoyourcomments anyinformationwithinthisdocumentthatyoufeeliswrong,unclearormissingatall?yourfeedbackwillhelpustocontinuously improvethequalityofthisdocument.pleasesendyourproposal(includingareferencetothisdocument)to: erratum@infineon.com publishedby infineontechnologiesag 81726mnchen,germany ?2017infineontechnologiesag allrightsreserved. legaldisclaimer theinformationgiveninthisdocumentshallinnoeventberegardedasaguaranteeofconditionsorcharacteristics (beschaffenheitsgarantie). withrespecttoanyexamples,hintsoranytypicalvaluesstatedhereinand/oranyinformationregardingtheapplicationofthe product,infineontechnologiesherebydisclaimsanyandallwarrantiesandliabilitiesofanykind,includingwithoutlimitation warrantiesofnon-infringementofintellectualpropertyrightsofanythirdparty. inaddition,anyinformationgiveninthisdocumentissubjecttocustomerscompliancewithitsobligationsstatedinthis documentandanyapplicablelegalrequirements,normsandstandardsconcerningcustomersproductsandanyuseofthe productofinfineontechnologiesincustomersapplications. thedatacontainedinthisdocumentisexclusivelyintendedfortechnicallytrainedstaff.itistheresponsibilityofcustomers technicaldepartmentstoevaluatethesuitabilityoftheproductfortheintendedapplicationandthecompletenessoftheproduct informationgiveninthisdocumentwithrespecttosuchapplication. information forfurtherinformationontechnology,deliverytermsandconditionsandpricespleasecontactyournearestinfineon technologiesoffice( www.infineon.com ). warnings duetotechnicalrequirements,componentsmaycontaindangeroussubstances.forinformationonthetypesinquestion, pleasecontactthenearestinfineontechnologiesoffice. theinfineontechnologiescomponentdescribedinthisdatasheetmaybeusedinlife-supportdevicesorsystemsand/or automotive,aviationandaerospaceapplicationsorsystemsonlywiththeexpresswrittenapprovalofinfineontechnologies,ifa failureofsuchcomponentscanreasonablybeexpectedtocausethefailureofthatlife-support,automotive,aviationand aerospacedeviceorsystemortoaffectthesafetyoreffectivenessofthatdeviceorsystem.lifesupportdevicesorsystemsare intendedtobeimplantedinthehumanbodyortosupportand/ormaintainandsustainand/orprotecthumanlife.iftheyfail,itis reasonabletoassumethatthehealthoftheuserorotherpersonsmaybeendangered. vphase gate charge waveforms

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